This invention is in the field of integrated circuits, and is more specifically directed to analog switched-capacitor circuits utilizing operational amplifiers.
A common building block in modern analog or mixed-signal analog electronic circuits is the operational amplifier. As is fundamental in the art, operational amplifiers can be readily implemented into analog circuits for performing a wide range of functions, including analog multiplication, analog integration, active filtering, and analog-to-digital conversion, to name a few. These widely ranging functions derive from the ideal characteristics of an operational amplifier (or “op amp”), namely infinite open loop gain, infinite input impedance, and zero output impedance. These ideal characteristics are used to advantage in conventional feedback op amp implementations, resulting in a “virtual” ground at the input (for finite voltage at the output, with infinite gain), and in the capability of the ideal op amp to generate high output current from zero input current.
An important class of circuits that are based on op amp realizations are switched-capacitor circuits. In general, switched-capacitor circuits involve the switching of charge among capacitors, for example from an input capacitor to a downstream capacitor or capacitor network or to an op amp input. Switched-capacitor circuits use the transfer of charge among capacitors rather than the switching of current through resistors, to accomplish the circuit functions. Switched capacitor circuits are particularly attractive in modern integrated circuits, because of the ability of the manufacturing technology to physically construct high-quality capacitors in relatively small integrated circuit “chip” area; in contrast, integrated circuit resistors tend to occupy a great deal of chip area, and are difficult to fabricate with precise resistance values.
FIG. 1 illustrates a first example of a conventional op amp circuit, specifically a sample-and-hold circuit. The function of this circuit is to drive an output voltage Vout that corresponds to a sample of an input voltage Vin. In this circuit, op amp 2 has its non-inverting input biased to ground and its inverting input connected to one plate of capacitor C at a node that is connected to ground through pass switch SB. The other plate of capacitor C is connected to receive input voltage Vin through pass switch SA, and the output of op amp 2 through pass switch SC. Pass switches SA, SB are clocked to be closed during clock phase Φ1, while pass switch SC is clocked to be closed during clock phase Φ2. Clock phases Φ1, Φ2 are non-overlapping clock phases, as shown in FIG. 1.
In operation, during “sample” clock phase Φ1, input voltage Vin charges capacitor C through closed pass switch SA, with pass switch SB connected to ground. During “hold” clock phase Φ2, pass switches SA, SB open, and pass switch SC closes. Because the non-inverting input of op amp 2 is at virtual ground for a finite output voltage Vout, and because pass switch SC has now connected capacitor C into the feedback loop, output voltage Vout equals the input voltage Vin (because of the inverting by op amp 2). Op amp 2 maintains this output voltage Vout until the next sample and hold period.
FIG. 2 illustrates another conventional op amp circuit, which in this case is a switched-capacitor residual gain generator as used in a pipelined multiplying-digital-to-analog converter (MDAC) circuit. The function of the circuit of FIG. 2 is to derive an output signal Vout that depends upon the difference (i.e., residual) between an input voltage Vin and a reference voltage VDAC. In this example in which the pipeline has 1 bit or 1.5 bits per stage, the output voltage Vout is intended to be twice the difference between input voltage Vin and a reference voltage VDAC/2, where voltage VDAC is the unipolar full scale voltage of the pipelined MDAC. In this circuit, pass switches S1, S2 each receive input voltage Vin on one side, and are connected to another side to a first plate of respective capacitors CA, CB. Capacitors CA, CB are preferably of the same capacitance value. The other plates of capacitors CA, CB are connected together, and to an inverting input of op amp 4 via pass switch S5; these capacitor plates are also connected to ground via pass switch S6. The first plate of capacitor CA is connected to receive reference voltage VDAC via pass switch S3, while the first plate of the capacitor CB is connected to the output of op amp 4 via pass switch S4. Pass switches S1, S2, and S6 are clocked to be closed during clock phase Φ1, while pass switches S3, S4, and S5 are clocked to be closed during clock phase Φ2. Clock phases Φ1, Φ2 are non-overlapping clock phases, as shown in FIG. 1.
In operation during “sample” clock phase Φ1, pass switches S1, S2, and S6 are closed, and pass switches S3, S4, S5 are open. Pass switches S1, S2 connect the input voltage Vin to capacitors CA, CB; the opposite plates of capacitors CA, CB are connected to ground by the closed state of switch S6. Capacitors CA, CB thus both charge to input voltage Vin during this clock phase. In clock phase Φ2, pass switches S1, S2, and S6 are open, and pass switches S3, S4, and S5 are closed. During this clock phase, the capacitor CB becomes the feedback capacitor, and capacitor CA receives the reference voltage VDAC. To the extent that reference voltage VDAC differs from input voltage Vin, charge sharing between capacitors CA and CB occurs. One can analyze the circuit by equating the sum of the charge on capacitors CA and CB during clock phase Φ1 with the sum of the charge on these capacitors during the next clock phase Φ2. In other words:−VinCA−VinCB=−VoutCB−VDACCA  (1)where the positive polarity sign of the charge on capacitors CA, CB points toward the inverting input of op amp 4, at virtual ground. Solving for output voltage Vout, and assuming identical capacitance C for capacitors CA and CB:
                              V          out                =                  2          ⁢                      (                                          V                in                            -                                                V                  DAC                                2                                      )                                              (        2        )            In this manner, the circuit of FIG. 2 generates an output that depends on a difference input signal. This residual gain stage is especially useful in multiplying DAC circuits, as known in the art.
Modern circuit design concepts and manufacturing technology have enabled the construction of conventional op amps that approach these ideal characteristics, with very high gains, very high input impedance, and very low output impedance. To the extent that the actual realization of modern op amps fall short of the ideal characteristics, however, error is introduced into the circuit. For example, the necessarily finite gain of the op amp is typically reflected by a voltage at the op amp input that is not at ground, but is instead at a voltage inversely proportional to the finite gain. This defeats the “virtual” ground assumption for the ideal op amp, and thus introduces error into the circuit. This source of error is typically referred to in the art as the “finite gain effect”.
In addition, the switching speed of conventional op amps is also not instantaneous, which also introduces error into the circuit.
It is well known in the art that conventional op amp designs involve a tradeoff between switching speed and gain, such that a high switching speed can only be attained by sacrificing op amp gain, and vice versa. Highly precise analog circuits, such as multiplying DACs, thus involve this tradeoff between precision (typically reflected in the number of bits of precision in the conversion) and switching speed.
Because of these effects, the circuit application must either tolerate non-ideal op amp characteristics, or circuit techniques must be developed to reduce the effect of these non-ideal characteristics. Previous circuit approaches to the reduction of finite gain effects are known in the art.
Nagaraj et al., “Reduction of the finite-gain effect in switched-capacitor filters”, Electron. Lett., Vol. 21 (July 1985), pp. 644–645; and Nagaraj et al., “Switched-Capacitor Circuits with Reduced Sensitivity to Amplifier Gain”, IEEE Transactions on Circuits and Systems, Vol. CAS-34, No. 5 (May 1987), disclose examples of these previous circuit approaches for reducing the finite gain effect. In these circuits, a correction for the finite gain effect is derived in a first, sample, clock phase, and then applied to the op amp in the second clock phase. These approaches each rely on the input voltage being stable over both clock phases of operation. If the input voltage changes between phases, however, the correction is not accurate without including a third clock phase to obtain the exact correction. Accordingly, it is believed that the performance of these known op amp circuits is limited.